Today's integrated circuits include a vast number of devices. Smaller devices are key to enhance performance and to improve reliability. As MOS (Metal Oxide Semiconductor Field-Effect-Device, a name with historic connotations meaning in general an insulated gate Field-Effect-Device) devices are being scaled down, the technology becomes more complex and new methods are needed to maintain the expected performance enhancement from one generation of devices to the next.
Silicon MOS scaling has become a major challenge in the semiconductor industry. Traditional techniques start to fail in reducing certain undesirable physical effects as device dimensions shrink down to the nanometer regime. For example, anti-punchthrough or halo implantation is used to reduce the short-channel effects. However, the abrupt doping profiles are difficult to achieve due to temperature enhanced diffusion, and these highly doped channels or pocket implant regions not only increase junction capacitance and band-to-band tunneling, but also degrades carrier mobility in the channel.
Band-gap engineering, namely introducing new materials into Si processing with different energy bands than Si, gives an important additional degree of freedom in device design. Among such new materials the SiGe alloy is one of the prominent members. The growth of high-quality compressively strained SiGe material by molecular beam epitaxy (MBE), or various types of chemical vapor deposition (CVD), allows incorporation of band-gap engineering concepts into a mature silicon technology.
A novel way to reduce short-channel effects is to have a built-in energy barrier at the source/body junction. As the height of the heterojunction barrier does not depend on the applied bias, it can resist the drain induced barrier lowering (DIBL). The band offset provided by SiGe heterojunction is mostly in the valence band, and it is very suitable for using such an effect for PFETs. (In the following the terms PFET and PMOS, as well as the terms of NFET and NMOS will used interchangeably.) Heterojunction MOSFETs (HJMOSFETS) have been disclosed, for example, in U.S. Pat. No. 6,319,799 B1 “High Mobility Heterojunction Transistor and Method” by Q. Ouyang, et al. and in a simulation study in “A Novel Si/SiGe Heterojunction pMOSFET with Reduced Short-Channel Effects and Enhanced Drive Current,” IEEE Transactions on Electron Devices, V. 47, p. 1943 (2000), by Q. Ouyang, et al. This latter reference showed that the SiGe/Si heterojunction and the dopants metallurgical junction have to coincide with each other to a relatively high precision, or the p-dopant has to be contained within the SiGe regions, in order to maintain the valance band offset between the source and body. Only when such precision is achieved can the heterojunction be effectively used to reduce the off state leakage and short-channel effects. Hitherto there was no method to give the desired coincidence of the heterojunction and the metallurgical junction, and no lateral device structure with such coincidence has been disclosed.